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MATLAB program for OFDM generation and reception
This is a simple MCM communications system. The code is pretty self-explanatory. Here I have not used the cyclic prefix.
Transmitter End:
1. Generate random serial data with M symbols (RAND
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pie编码器,将串行数据并行输出的一种常用编码-pie encoder, parallel to serial data output of a common coding
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并串转换器：将并行输入的信号以串行方式输出，这里要注意需先对时钟进行分频，用得到的低频信号控制时序，有利于观察结果（可以通过L灯观察结果）-And series converter: the input signal in parallel to serial output, where attention should be paid to the need to carry out first clock frequency, low-frequency signals received b
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并/串转换器即并行输入、串行输出转换器，例如一个8bit输入的并/串转换器，输出时钟频率是输入时钟频率的8倍，输入端一个时钟到来，8个输入端口同时输入数据；输出端以8倍的速度将并行输入的8bit串行输出，至于从高位输出还是从低位输出，可以再程序中指定。-And/or parallel series converter input, serial output converter, for example, a 8bit input and/series converter, the output
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This file contains the Parallel to Serial conversion. This is the top module where we can change the code. The other part of this file is Parallel to Serial controller i,e P2S_SM
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This file contains the state machine which has the control signals required for the parallel to serial conversion-This file contains the state machine which has the control signals required for the parallel to serial conversion....
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This file recieves the serial data from the UART and forward to Serial To Parallel module
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parallel to serial shift register
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parallel to serial experiment and string
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good version of soft Demapping QPSK : LLR computation using Euclidian distance approache, Parallel-to-Serial converter, needs I and Q componets of QPSK symbols at the input
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soft Demapping 8PSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, needs I and Q componets of 8PSK symbols at the input
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corrected version of Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, needs I and Q componets of QPSK symbols at the input
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Demapping 8PSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, Hard decision, needs I and Q componets of 8PSK symbols at the input
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本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
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This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
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parallel to serial data converter using VHDL
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16位并行转串行译码器Verilog，以及synopsis综合结果，行为级、门级网单，均已通过仿真验证-16bit parallel to serial decoder and aynthesis result
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16QAM的matlab仿真,非常有用,包括Bit mapping,modulation and demodulation,Bit demapping,Parallel to serial conversion,Bit error ratio-16QAM the matlab simulation, very useful, including Bit mapping, modulation and demodulation, Bit demapping, Parallel to serial
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this code is designed to perform parallel to serial operation it is very essential in every design
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595比较器的典型使用方法：驱动LED数码管的函数（并行转串行）-The typical comparator 595 to use: drive LED digital tube function (parallel to serial)
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